This relates generally to integrated circuits, and more particularly, to integrated circuits with flip-flops.
Integrated circuits often include circuits such as scan chain circuits. A typical scan chain includes flip-flops that are connected in a chain. A scan chain having a series of flip-flops connected in this way may sometimes be referred to as a shift register.
The flip-flops are controlled by a clock signal. Each flip-flop has a master latch and a slave latch. The master latch is enabled during a low clock phase of the clock signal (i.e., when the clock signal is pulsed low) while the slave latch is enabled during a high clock phase of the given clock signal (i.e., when the clock signal is pulsed high).
A pair of consecutive flip-flops in the scan chain may receive clock signals that are skewed with respect to each other. For example, consider a scenario in which a first flip-flop in the pair of flip-flops receives a given clock signal, and a second flip-flop in the pair of flip-flops receives a clock signal that is skewed from the given clock signal. In this example, the (skewed) clock signal that is received by the second flip-flop may exhibit a delayed rising clock edge relative to the rising clock edge of the given clock signal.
A problem arises when the output of the first flip-flop changes value before the rising clock edge of the skewed clock signal. This will cause the second flip-flop to latch an incorrect value during scan operations. Circuit malfunctions of this type are sometimes referred to as hold time violations.
It would be desirable to be able to provide improved flip-flops such as flip flips that avoid hold time violations.